With the advent of sub-micron technology, the device dimensions are decreased so as to be suitable in low cost and low power applications. Also, circuit designing for standard protocols has become more challenging. Sub-micron technology devices cannot tolerate high-voltage because of reliability issues. The gate-oxide breakdown voltage and/or the punch-through between source and drain typically define the voltage of a particular technology. To meet the standard protocols' electrical specifications, interface circuits must work at high voltages (e.g. 5V, 3.3 V etc) with high reliability. One notable problem in interfacing low-voltage circuitry with high-voltage circuitry is that if the voltage applied to the low-voltage circuitry gets too high, some devices may experience temporary or even permanent damage. The gate-oxide stress causes threshold voltage to fluctuate because of tunneling effect—moreover, device lifetime deteriorate.
At the process level, the high-voltage tolerant transistors can be fabricated by increasing gate oxide and an extended drain scheme. These devices increase the fabrication cost because of extra masks required to make device level tune in the same CMOS baseline process. Another disadvantage is performance degradation.
FIG. 1 shows a schematic diagram of a conventional input buffer 100 with an input IN and output OUT, for 3.3 volt devices. VDDS=3.3 volt.
FIG. 2 is a schematic diagram of a 5V tolerant input buffer operating at 3.3V nominal voltage. VDDS=3.3 volt. All the devices are in 3.3V technology. IN is connected to the drain of MOSFET M1, which translates the input signal to a lower voltage at node 1 for safe operation of the buffer 200. When IN goes as high as 5V, node is clamped to (VDDS−Vt), so all the devices are safe. Because the substrate bias effect Vt of transistor M1 is high, node 1 voltage is comparatively low. This may cause M2 to be in weak inversion or in strong sub-threshold region. So, the conventional input buffer 200 will consume DC power, which is more serious in 0.13 μm technology because Vt is less, when signal on pad is high. Moreover, this structure cannot be used when device is of 2.5V and is operating at 3.3V.
FIG. 3 is another schematic of 5V tolerant input buffer 300 in 3.3V technology. VDDS=3.3 volt. MOSFET 2 and an NMOS are used to clamp high voltage at the input. To avoid turn ON of M2 (because of difference {VDDS−V2}>|VtM2|), a weak pull-up structure consisting of two series transistors 4 (PMOS) and 5 (NMOS) has been used. It will pull the node 120 to VDDS level provided node 110 is at (VDDS+Vt5). It happens only when IN starts rising above VDDS. When IN reaches VDDS+|Vt1|, transistor 1 turns on and node 110 is charged to a voltage equal to IN. When IN rises to 5V, node 110 also gets charged to 5V. Transistor 3 remains OFF because the gate and source voltages are at the same level. Transistor 5 turns-on strongly and node 120 is pulled to VDDS (3.3V nominal). When the voltage at IN reaches ground level, node 110 discharges to (VDDS+|Vt1|) volt only through transistor 1. Transistor 3 pulls node 110 to |Vt3| level so that transistor 5 (NMOS) is OFF.
The circuit in FIG. 3 cannot be used for 2.5V devices operating at 3.3V because the gates of 1 and 2 cannot be connected to VDDS (3.3 Volt) directly. Moreover, 5V cannot be directly applied to the gate of 2.5V devices because the gate-bulk voltage (Vgb) for NMOS (5) is significant (5.0V) to deteriorate the oxide.
The circuit in FIG. 4 is another 5V tolerant input buffer structure using 2.5V devices designed for 2.5V operation. VDDS=2.5 volt. This structure is able to tolerate input signal of 5V while operating safely. In normal mode LPN is connected to ground. Transistors M1 and M4 form a source follower structure where M4 acts as a resistor. Node 1 never exceeds VDDS level. M9 has been added to speed-up the buffer when IN makes transition from high to low, because the size of transistor M4 is less (to reduce the dc power consumption in normal mode). Transistors M6 and M7 have been used to provide buffering at the output. This structure also works perfectly without stressing any device. But the buffer cannot be used for low power and 3.3 Volt operations. In normal mode it consumes dc current and an extra mode control signal is required.
U.S. Pat. Nos. 5,952,848 and 6,236,236 are referred to for additional reference.
Since for standard protocols, the voltage levels (usually 3.3V and 5V) are fixed, an input buffer is required which can tolerate signal of 5V at the receiver input and can be implemented with low-voltage technology.
It is therefore desirable to have an input buffer circuit, which is capable of receiving a high voltage without experiencing degradation of gate oxide lifetime. It would further be desirable if such input buffer does not increase the process complexity and is implemented in the recent technology while working at higher supply voltage (e.g. 3.3 volt nominal).